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io.github.SiliconAnalysts/silicon-analysts
Dated, sourced semiconductor data: chip costs, HBM/wafer pricing, fab capacity, policy, forecasts.
biocontext
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glama
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mcp.so
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nerq
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pulsemcp
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smithery
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Pure-function chip cost estimator. Given die dimensions (mm), process node, and optional packaging/HBM parameters, returns: estimatedChipCost (USD), dieArea (mm²), grossDiesPerWafer, frontendYield (%), totalYield (%), and a costBreakdown {waferCostPerGoodDie, packagingAndTestCost, hbmCost, marginCost}. USE THIS for: hypothetical chip cost modeling, sensitivity analysis, fabless tapeout decisions. DO NOT USE for: published cost of an existing accelerator (use get_accelerator_costs); wafer pricing only (use get_wafer_pricing). Required: dieWidth, dieHeight (1–33 mm reticle limit). Errors with INVALID_PARAMS if outside bounds. processNode defaults to tsmc-n5; valid nodes via get_wafer_pricing. Estimates are directional ±15–20%. Optional energy adder: pass energyRegion (texas|ohio|arizona|china|korea|taiwan|germany) to get a conditional `energy` block — regional manufacturing-electricity cost per die (SA estimate; wafer price already embeds foundry energy, so treat it as a scenario delta). energyFacilityOverhead=false drops the ~1.75× facility multiplier. Optional substrate scenario: pass substrate=panel-310x310 to model CoPoS panel-level assembly — applies the midpoint of Yole's realistic 20–30% panel cost-savings band to the packaging cost ONLY (silicon GDPW unchanged; panels are back-end). Conditional `substrateScenario` block + SA-scenario meta note. TSMC CoPoS: pilot ~June 2026, mass production 2028–29 — a forward-looking scenario, not a quote.
Heuristic chip manufacturing LEAD TIME estimator (MANUFACTURING CYCLE TIME). Given total mask layers (or a processNode to default them), foundry utilization % (optional — defaults from live foundry-allocation data), and packagingType, returns min/max bands: fabDays, fabWeeks, packagingWeeks, totalWeeks, plus effectiveDpml (days per mask layer), the operating-curve weight, a resolved-inputs echo, assumptions, methodology, and public-source citations. USE THIS for: "how long to manufacture this chip" — wafer-fab cycle time + packaging assembly/test time for hypothetical chips; cycle-time sensitivity to fab utilization or packaging class (conventional vs flip-chip vs CoWoS). DO NOT USE for: booking windows / allocation lead time — how long until a booked-out foundry STARTS wafers, publicly 52–156+ weeks at N3-class nodes and CoWoS (use get_foundry_allocation); chip cost (use calculate_chip_cost / get_accelerator_costs). Provide maskLayers (integer 10–200) or processNode (tsmc-n3 | tsmc-n5 | tsmc-n7 | tsmc-28 | samsung-3nm | samsung-5nm | intel-16). packagingType accepts coarse classes (conventional | flip-chip | cowos, default flip-chip) or any platform packaging id (fc-bga, wirebond-bga, cowos-l, copos, ...). Utilization ≤80% settles at the best-case band; ≥95% converges to the worst-case bound (FabTime operating-curve shape). Heuristic from public DPML benchmarks — directional, confidence LOW, not a foundry quote. Cite as "Silicon Analysts — Lead Time Estimator".
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