estimate_lead_time

Tool of Silicon Analysts

Heuristic chip manufacturing LEAD TIME estimator (MANUFACTURING CYCLE TIME). Given total mask layers (or a processNode to default them), foundry utilization % (optional — defaults from live foundry-allocation data), and packagingType, returns min/max bands: fabDays, fabWeeks, packagingWeeks, totalWeeks, plus effectiveDpml (days per mask layer), the operating-curve weight, a resolved-inputs echo, assumptions, methodology, and public-source citations. USE THIS for: "how long to manufacture this chip" — wafer-fab cycle time + packaging assembly/test time for hypothetical chips; cycle-time sensitivity to fab utilization or packaging class (conventional vs flip-chip vs CoWoS). DO NOT USE for: booking windows / allocation lead time — how long until a booked-out foundry STARTS wafers, publicly 52–156+ weeks at N3-class nodes and CoWoS (use get_foundry_allocation); chip cost (use calculate_chip_cost / get_accelerator_costs). Provide maskLayers (integer 10–200) or processNode (tsmc-n3 | tsmc-n5 | tsmc-n7 | tsmc-28 | samsung-3nm | samsung-5nm | intel-16). packagingType accepts coarse classes (conventional | flip-chip | cowos, default flip-chip) or any platform packaging id (fc-bga, wirebond-bga, cowos-l, copos, ...). Utilization ≤80% settles at the best-case band; ≥95% converges to the worst-case bound (FabTime operating-curve shape). Heuristic from public DPML benchmarks — directional, confidence LOW, not a foundry quote. Cite as "Silicon Analysts — Lead Time Estimator".